Hey people.
So here's a project I'm currently working on. It's a 8 bit CPU or as some people know as computer (I personally don't like this term since it's not technically correct). It's currently being built on the redsignal server on the Phrozencookie network.

The CPU will be built vertically using vertical logic compoents. Currently it only has an 8 bit CCA ALU and a 7 byte pseudo dual read register (pseudo cause it's actually single read but has 2 registers paired together to act as a single one).

I will have the ISA (instruction set architecture) completed on a google doc spreadsheet and will post it on here when finished.

The CPU may or may not be pipelined, most likely not but it's still early enough for me to do that if I want to but it'll take longer if I do. The CPU at the end will be programmed to run the Fibonacci sequence and/or Multiplication. (It will be turing complete so technically any program can be written on it but those are just for demonstration purposes). I also plan on including a GPU interface for line drawing and point plotting and will probably run the bresenham line drawing algorithm for that. It will also have a decimal display for another output. As of now, this CPU will probably be really slow lol but if i pipeline it then it'll probably be decent. Anyway more updates to come!

Components and descriptions

ALU - Arithmetic logic unit - A logic unit built using an adder and other modifications in order to simulate different types of logic operations (such as OR, AND, XOR, etc) (IRL ALUs don't normally have modification lines on adders to change logic but usually use muxes in order to move the inputs to logic arrays. In MC it's easier to modify the adder itself for logic modification.. This ALU specifically has !a, !b, OR, XNOR (flood carry), and carry in. Also by using Demorgan's theorum the ALU can simulate any other logic gate which has a 3 to 1 output ratio by using the OR function since OR has a 3 to 1 output ratio already. This ALU is made using a CCA (carry cancel adder) designed by Koyarno from the Open Redstone Engineers server. The ALU modifications are my own mostly but inspired by the redstone youtuber Bennyscubed who made a video of making an ALU based on Koyarno's design (ALU and CCA videos). Most of the ALU is my own but the right shift logic i took from benny slightly.

Registers - A form or memory which is small but fast. It is immediately used by the ALU to process data quickly without needing to reach far for the larger ammounts of memory in Cache or RAM. Registers are essentially a collection of d flip flops (data flip flops) which can save data inputted and output the saved data to be processed elsewhere. This design is based on a design that I don't know the original creator of but was featured by Bennyscubed again in his CPU tutorial series (Register video).