This is a compact decoder using rails to transmit data of height 6, with 13 and lenght 20 for a 8 bit decoder with currently 16 outputs.

4rt cycle
7rt delay from imput observer to output comparator
Requires clock signal
1 wide tilable
6 by (5+1/bit) by (4+1/output)
Minimal pistons

The decoder can run at 4rt (redstone tick) and produces 2rt pulses each time. Meaning that even if the same output is selected continuesly, it will give a 2rt pulse every time. There is a delay of 1rt every 10 blocks.

Operates on the fact that comparators require 2rt to activate. 1st, only the rail line of the selected output will not be activated. Everything else will be activated an meet the comparator with the clock signal at the same time, hence only 1rt, no activation. 2nd, 1rt after all other rails are activated, a clock signal will activate all rails including selected output. The other rails will thus remail on and not update observers again, however the selected output will. This selected output with a delayed activation will meet the comparator 1rt after the clock, producing 2rt, hence activation. Repeater is in place before comparator to prevent update order problems. The repeater can be removed but not recomended.

There is a test ROM and a control unit to test decoder