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UTD Main Thread
Created by Jontis_00 for the UTD
This is a vertical memory cell tileable with 1 space inbetween.
It comes with 4 inputs lines for: Reseting memmory, enable writing for 0's, enable writing for 1's, send stored data.
It is very easy to wire inputs and outputs.
The schematic contains 8 cells and instructions of what each line dose.
UTD Main Thread
Created by Jontis_00 for the UTD
This is a vertical memory cell tileable with 1 space inbetween.
It comes with 4 inputs lines for: Reseting memmory, enable writing for 0's, enable writing for 1's, send stored data.
It is very easy to wire inputs and outputs.
The schematic contains 8 cells and instructions of what each line dose.
1 Update Logs
Update #1 : by UTD Projects 07/17/2011 10:27:29 pmJuly 18, 2011 @ 2:27 am UTC
-Initial Release
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