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Communities/Redstone CPU design Tips & tricks
nnewram
• 08/06/2018 1:00 am
• Level 1 : New Miner

oh and if you want to see my stuff its all on that server, its kinda spread out on diffrent plot as a almost always collab with someone if the project is gonna be big. Me(ign: nnewram) HyperXti made a 16 bit mult like 3 days ago 45 tick, using 2tick serial hex. It is one of a kind as it uses modulus for multiplication oh and Creds to Don!!!!! He came up with the logic behind it.

so you can do "/p v nnewram" "/p v hyperxti 2" and "/p v maxssho13" becouse thats where my shids at
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Communities/Redstone CPU design Tips & tricks
nnewram
• 08/06/2018 12:33 am
• Level 1 : New Miner

Well im not sure if you mean RAM as in Register blocks or if you are just talking about registers. I build vertically usually 8 bits but i currently have a WIP 16 bit gpu goin on so all the register cells sits stacked ontop of eachother. then i also stack them horizontally so i would have (usually) 7 * 8 bit registers in a 14*21 wide area and depending on if the registers are dual read or not they can have some difference in lenght. Oh and you could have A and B memory or just a dual read one with 2 output lines going to a flush latch that then goes into the ALU.

If you are speaking about RAM blocks then basically there are 3 scenarios
1. you have cache
2. you have cache and a pipline
3 you dont have cache

if you can read in a block(1 block is however many registers you have in your register file) at a time then you are all set buuuut say you have a pipeline then it becomes a bit trickier. i dont think i can explain that in this text tough so please join mc.openredstone.org for that info.

And the last case would be that you dont have any cache, then you just OR gate all the RAM's outputs into its correct bit bus and have that on the same line as the ALU output.

Dang that was a logn reply sorry for late response i didnt get any notification whatsoever
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