Dynamic Random Access Memory

Quick Overview

Capacity: 32 bytes
Least addressable unit: 1 byte
Dimensions: 207x87x21
Download: schematic (see link)

Overview

It has a capacity of 32 bytes which consists of 32 clusters of 1 byte each. You can read and write one byte at a time. We designed our DRAM for fast, efficient, and easy-stackable performance.
The schematic consists of a very simple control panel that controlls the whole system. The lowest 8 redstone lights represent the output read from memory. The 4 levers above select a memory cluster (that is 0-15). The button next to these levers is used to store data into memory. The uppermost 8 levers represent the data input that will be written when you press the button.
Note: the order of the input and output data bits is not important. Thus, if you want big endian bit order, you can swap the data lines.
Our 64 Byte RAM will come out soon.