Published Feb 20th, 2012, 2/20/12 6:05 am
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Creators of this project Medicijnman, and AdmBot.
Inspired by xDOTxMr's 1 Bit CPU. www.youtube.com/user/xDOTxMr
Dimensions: 28x58x9
INTRODUCTION
This processor/cpu is the first redstone computer machine we, AdmBot and Medicijnman, built and actually worked. Further on this post we will call our machine "processor".
Ofcourse we could make a 2 bit, or bigger CPU, but its much work, and since there are almost no 1 bit CPU's built in Minecraft, we builded one.
SUMMARY
Introduction
Specs
Redstone components
Instruction format
ISA
Registers
Example
SPECS
The processor has the following features:
- 2 1-bit registers
- 1 1-bit accumulator
- 8* opcodes
- ready flag (not very interesting tough)
- execution button (very usefull)
*) There are only 6 opcodes used; if you want you can add two another instructions to the ISA.
REDSTONE COMPONENTS
The processor has the following logical ports and redstone components:
- 3 RS NOR latches (1 latch for each register and 1 latch for accumulator)
- 3 to 8 decoder (opcode decoder)
- 5 piston check systems
- 2 2-to-1 muxs
- AND, NOT, OR, NOR, and XOR logic gates
- 1043 Redstone Dust Pieces
- 81 Repeaters
- 61 Redstone Torches
INSTRUCTION FORMAT
Each instruction has the same length (6 bits) with the following format:
XYZOOO
where:
XY is a register (see REGISTERS for binary names)
Z is one bit of data (the data bit used in opcode 000b)
OOO is the opcode (see ISA for all opcodes and instructions)
ISA
+--------+-------------+---------------+------------------------------------------+
| opcode | assembly | c instruction | in english |
+--------+-------------+---------------+------------------------------------------+
| 000b | MOVE Z, XY | XY = Z | Write Z to XY |
| 001b | MOVE XY, Acc| XY = Acc | Move Acc to XY |
| 010b | OR Acc, XY| Acc |= XY | OR Acc and XY and store result in Acc |
| 011b | XOR Acc, XY| Acc ^= XY | XOR Acc and XY and store result in Acc |
| 100b | NOT Acc | Acc = ~Acc | Invert Acc value and store result in Acc |
| 101b | AND Acc,XY | Acc &= XY | AND Acc and XY and store result in Acc |
| 110b | NOP | ; | No Operation |
| 111b | NOP | ; | No Operation |
+--------+-------------+---------------+------------------------------------------+
REGISTERS
The processor has 2 registers and an accumulator which are listed here:
Name, binary name, capacity, speed*
Register0, 00b, 1 bit, slow
Register1, 01b, 1 bit, normal
Accumulator, 10b or 11b, 1 bit, fast
*) This indicates how fast you can write data to this register; thus a register with a fast speed takes less ticks to write to than a normal or slow register.
EXAMPLE
Lets say we have the following c-program:
int a = 1;
int b = a & a;
a = a == 1 ? 0 : 1;
b = a & a;
If we write one command on each line we will get this:
int a = 1;
int b = a;
b &= a;
if (a == 1) {
a = 0;
} else {
a = 1;
}
b = a;
b &= a;
If we assemble the program we will get this:
MOVE 1, a
MOVE a, b
AND b, a
NOT a
MOVE a, b
AND b, a
If we convert this to our ISA we will get this:
MOVI 1b, %10
MOV %10, %01
AND %10, %01
MOV %10, %00
OR %10, %01
NOT %10
MOV %10, %01
OR %10, %00
AND %10, %01
If we convert this to machine code we will get this:
101000
010001
010101
000001
010010
000100
010001
000010
Inspired by xDOTxMr's 1 Bit CPU. www.youtube.com/user/xDOTxMr
Dimensions: 28x58x9
INTRODUCTION
This processor/cpu is the first redstone computer machine we, AdmBot and Medicijnman, built and actually worked. Further on this post we will call our machine "processor".
Ofcourse we could make a 2 bit, or bigger CPU, but its much work, and since there are almost no 1 bit CPU's built in Minecraft, we builded one.
SUMMARY
Introduction
Specs
Redstone components
Instruction format
ISA
Registers
Example
SPECS
The processor has the following features:
- 2 1-bit registers
- 1 1-bit accumulator
- 8* opcodes
- ready flag (not very interesting tough)
- execution button (very usefull)
*) There are only 6 opcodes used; if you want you can add two another instructions to the ISA.
REDSTONE COMPONENTS
The processor has the following logical ports and redstone components:
- 3 RS NOR latches (1 latch for each register and 1 latch for accumulator)
- 3 to 8 decoder (opcode decoder)
- 5 piston check systems
- 2 2-to-1 muxs
- AND, NOT, OR, NOR, and XOR logic gates
- 1043 Redstone Dust Pieces
- 81 Repeaters
- 61 Redstone Torches
INSTRUCTION FORMAT
Each instruction has the same length (6 bits) with the following format:
XYZOOO
where:
XY is a register (see REGISTERS for binary names)
Z is one bit of data (the data bit used in opcode 000b)
OOO is the opcode (see ISA for all opcodes and instructions)
ISA
+--------+-------------+---------------+------------------------------------------+
| opcode | assembly | c instruction | in english |
+--------+-------------+---------------+------------------------------------------+
| 000b | MOVE Z, XY | XY = Z | Write Z to XY |
| 001b | MOVE XY, Acc| XY = Acc | Move Acc to XY |
| 010b | OR Acc, XY| Acc |= XY | OR Acc and XY and store result in Acc |
| 011b | XOR Acc, XY| Acc ^= XY | XOR Acc and XY and store result in Acc |
| 100b | NOT Acc | Acc = ~Acc | Invert Acc value and store result in Acc |
| 101b | AND Acc,XY | Acc &= XY | AND Acc and XY and store result in Acc |
| 110b | NOP | ; | No Operation |
| 111b | NOP | ; | No Operation |
+--------+-------------+---------------+------------------------------------------+
REGISTERS
The processor has 2 registers and an accumulator which are listed here:
Name, binary name, capacity, speed*
Register0, 00b, 1 bit, slow
Register1, 01b, 1 bit, normal
Accumulator, 10b or 11b, 1 bit, fast
*) This indicates how fast you can write data to this register; thus a register with a fast speed takes less ticks to write to than a normal or slow register.
EXAMPLE
Lets say we have the following c-program:
int a = 1;
int b = a & a;
a = a == 1 ? 0 : 1;
b = a & a;
If we write one command on each line we will get this:
int a = 1;
int b = a;
b &= a;
if (a == 1) {
a = 0;
} else {
a = 1;
}
b = a;
b &= a;
If we assemble the program we will get this:
MOVE 1, a
MOVE a, b
AND b, a
NOT a
MOVE a, b
AND b, a
If we convert this to our ISA we will get this:
MOVI 1b, %10
MOV %10, %01
AND %10, %01
MOV %10, %00
OR %10, %01
NOT %10
MOV %10, %01
OR %10, %00
AND %10, %01
If we convert this to machine code we will get this:
101000
010001
010101
000001
010010
000100
010001
000010
| Progress | 100% complete |
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Have something to say?
Its a very interesting theoretical machine; unfortunately it's not Turing complete.
The reason can be seen in your example.. when you compiled "if (a == 1) {a = 0} else {a = 1}" as "NOT a"
That comparison and pair of declarations is equivalent to your atomic function 'NOT', however it illustrates the machines inability to branch; which is necessary to distinguish inputs.
You are absolutely right. We are planning to make a 2 bit processor with jump and branch instructions.
That machine will be probaly turing complete