This is not really a TRUE D-Flip Flop. When you have an input signal of FALSE and you pulse the clock input, this logic gate alters the output to TRUE for the duration of the clock pulse. When integrated with additional circuity on the output, it has the potential to cause unwanted operation.

In a real D-Flip flop the clock pulse will NOT alter the output UNLESS the input signal has changed since the output was last saved.

Those of you looking for a D-flip flop using pistons, beware of this caveat.

There is a vertical D-flip flop schematic that works correctly in all scenarios. However it is rather cumbersome to deal with as it requires 6 or more blocks vertical space with the clock input up high. It is a single block wide, which allows multiple gates to be stacked right next to each other. So if you can manage your inputs effectively, it allows you to create good data storage density as you multiply it out several times. it is possible to make X bits of storage in an X bit wide surface area.

Dang, good job making that tiny little bugger.