8
My First Major Redstone project, this is a 1-bit ALU designed for streaming data in bit pairs. Currently it has 2 bytes of ROM as input and 1 byte of serial memory as an output register. the ROM could be replaced with anything that inputs pairs of bits at an appropriate interval (currently 15 ticks) and the output memory could be lengthened arbitrarily. This ALU takes 133 ticks in total to perform an 8-bit operation. This may seem like a long time but given that with slight modification this ALU could perform operations of effectively any length it may be a useful trade off in some cases. To increase the length of the operation one must either increase the size of the input and output registers or remove them entirely and simply pulse the bit pairs through individually, resetting the carry in latch, then pulsing the carry swap piston and finally resetting the output carry latch between each pair, and at the end of the full operation resetting both the input and output carry latches.
Operations:
00 A AND B
01 NOT A(Gold)
10 A OR B
11 A ADD B
*Note: There are sets of 4 repeaters between cells in the output memory, each of these sets is set to 15 ticks except one that is set to 16, this is because of a delay in the input ROM that causes a 1 tick delay after 5 pairs of input bits, if the ROM is replaced with something without this delay then the extra delay in the output memory will need to be removed.
Operations:
00 A AND B
01 NOT A(Gold)
10 A OR B
11 A ADD B
*Note: There are sets of 4 repeaters between cells in the output memory, each of these sets is set to 15 ticks except one that is set to 16, this is because of a delay in the input ROM that causes a 1 tick delay after 5 pairs of input bits, if the ROM is replaced with something without this delay then the extra delay in the output memory will need to be removed.
2 Update Logs
Update #2 : by PyroCybin 04/06/2012 3:53:24 amApril 6, 2012 @ 7:53 am UTC
After Long last the adder is finished. entire ALU slowed to 15/16 ticks per bit pair or 133 ticks for a full 8 bit operation. it is likely the ALU can run at a higher clock speed with some modification.
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Have something to say?
I would like to hear about how it's going,
Do you plan on constructing a CPU, and if so, would you write about the Instruction set architecture ???
Can't wait to see this thing running in a computer : D
Especially Since... PytoCybin leaves his ALU constantly running!
Sounds good man : )
Multiple rising-edge signals can be jammed down a single cable... However they only have a noticable effect on pistons.
You can combine signals smoothly with a 1-tick repeater... But i'm pretty sure it's not possible to-do instantly; even with a full size instant-repeater.
Good luck!
You have alot of potential +1 and sub.