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I've tried to make a (relatively) fast and stackable memory cell using pistons (mostly for the addressing, the memory cell itself is a D-latch made from pure redstone) and built a 256-byte RAM with it.
The download contains both the 256 byte RAM and a dual memory cell (one cell is mirrored to share the data paths).
(If you are using WorldEdit, paste the 256 byte schematic twice, otherwise some blocks are missing)
The cells are addressed in a matrix; two active, intersecting brown signal lines (named x and y in the logic diagram) enable the cell.
Red: data output
Green: address input
light blue, orange and light green indicate LSB.
Yellow: write enable
Purple: clear RAM (long pulse needed)
The download contains both the 256 byte RAM and a dual memory cell (one cell is mirrored to share the data paths).
(If you are using WorldEdit, paste the 256 byte schematic twice, otherwise some blocks are missing)
The cells are addressed in a matrix; two active, intersecting brown signal lines (named x and y in the logic diagram) enable the cell.
Additional Notes
Blue: data inputRed: data output
Green: address input
light blue, orange and light green indicate LSB.
Yellow: write enable
Purple: clear RAM (long pulse needed)
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1 Update Logs
Update #1 : by zaubara 04/20/2012 5:35:22 pmApril 20, 2012 @ 9:35 pm UTC
added the logic diagram for one bit
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rundje
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RicoPico1516
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