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Cloud Computer
The Minecraft Cloud Computer is a fully functional 16 bit computer. It is very similar to a modern CPU in design with the fallowing amazing features.
* 27 Instructions.
* 10 ALU operations.
* 8 general purpose registers. Can store addresses or data.
* Instruction pipeline (Instruction prefetch similar to the 68K CPU)
Functional Assembler program that will assemble assembly prgrams into machine code. (Separate python program)
* 16 bit words
* 128 words of RAM (256 bytes)
* 64 words of ROM
* 64 free addresses for future I/O expansion such as BCD displays, user input, tape drives, etc.
* Load and store register indirect instructions are available. (Pointers)
* Does all ALU operations in 1 clock cycle. IE. %r0 = %r1 + %r2 is possible in one cycle with pipelining.
;
;
; Set all RAM to -1
;
;
; %r0 constant -1
; %r1 write pointer.
; %r2 constant 1
; %r3 constnat 256
cp %r0 -1
cp %r1 [minMem] ; 128 is the first byte of RAM.
; RAM goes from 128 to 255
cp %r2 1
cp %r3 [maxMem] ; Load from ROM. load immediat can only load -128 to 127 with sign extension
loop: cp [%r1] %r0 ; Copy -1 to the %r1 pointer
add %r1 %r1 %r2 ; Add 1 to the write pointer
ucmp %r1 %r3
jl loop ; jump while %r1 < %r3
end: jmp end
maxMem: .num 256
0 minMem: .num 128
; Assembled output
;00 00001 000 11111111
;01 00010 001 00001010
;02 00001 010 00000001
;03 00010 011 00001001
;04 00101 000 00001000
;05 10000 001 00001010
;06 11000 000 00001011
;07 00111 110 00000100
;08 00110 000 00001000
;09 00000001 00000000
;10 00000000 10000000
You can download the assembler from:
http://pastebin.com/FbbCfcwU
The Minecraft Cloud Computer is a fully functional 16 bit computer. It is very similar to a modern CPU in design with the fallowing amazing features.
* 27 Instructions.
* 10 ALU operations.
* 8 general purpose registers. Can store addresses or data.
* Instruction pipeline (Instruction prefetch similar to the 68K CPU)
Functional Assembler program that will assemble assembly prgrams into machine code. (Separate python program)
* 16 bit words
* 128 words of RAM (256 bytes)
* 64 words of ROM
* 64 free addresses for future I/O expansion such as BCD displays, user input, tape drives, etc.
* Load and store register indirect instructions are available. (Pointers)
* Does all ALU operations in 1 clock cycle. IE. %r0 = %r1 + %r2 is possible in one cycle with pipelining.
Instruction set (Best viewed in a mono-spaced font)
MISC Operations
00 00000--- -------- nop
01 00001ccc iiiiiiii cp r0 addr; Load iiiiiiii into register ccc;
02 00010ccc aaaaaaaa cp r0 [addr]; Load whatever is in address aaaaaaaa into register
03 00011ccc --aaa--- cp r0 [r1]; Load something from the address in register aaa into register ccc
04 00100ccc aaaaaaaa cp [addr] r0; Store something in register ccc into address aaaaaaaa. (Not implemented)
05 00101ccc -----aaa cp [r1] r0; Store something in register ccc into the address stored in register aaa.
06 00110000 aaaaaaaa jmp addr; Jump to address aaaaaaaa.
07 00111000 aaaaaaaa jz addr; Jump if zero
07 00111001 aaaaaaaa jnz addr; Jump if not zero
07 00111010 aaaaaaaa je addr; Jump if equal
07 00111011 aaaaaaaa jne addr; Jump if not equal
07 00111100 aaaaaaaa jg addr; Jump if greater than
07 00111101 aaaaaaaa jge addr; Jump if greater than or equal to
07 00111110 aaaaaaaa jl addr; Jump if less than
07 00111111 aaaaaaaa jle addr; Jump if less than or equal to
08 01000rrr aaaaaaaa jsr addr; Jump to subroutine. Save return address into r
09 01001--- --rrr--- rts; Return from subroutine. Return to address in r
10 01010--- -------- nop
11 01011--- -------- nop
12 01100--- -------- nop
13 01101--- -------- nop
14 01110--- -------- nop
15 01111--- -------- nop
ALU Operations
16 10000ccc --aaabbb add r0 r1 r2 Add
17 10001ccc --aaabbb and r0 r1 r2 And
18 10010ccc --aaabbb or r0 r1 r2 Or
19 10011ccc --aaabbb xor r0 r1 r2 Xor
20 10100ccc --aaa--- not r0 r1 Not
21 10101ccc --aaa--- rsh r0 r1 RShift
22 10110ccc --aaa--- rshx r0 r1 XRShif
23 10111ccc --aaa--- cp r0 r1 Copy
24 11000--- --aaabbb scmp r0 r1 Signed Compare
25 11001--- --aaabbb ucmp r0 r1 Unsigned Compaire
26 11010--- -------- nop
27 11011--- -------- nop
28 11100--- -------- nop
29 11101--- -------- nop
30 11110--- -------- nop
31 11111--- -------- nop
00 00000--- -------- nop
01 00001ccc iiiiiiii cp r0 addr; Load iiiiiiii into register ccc;
02 00010ccc aaaaaaaa cp r0 [addr]; Load whatever is in address aaaaaaaa into register
03 00011ccc --aaa--- cp r0 [r1]; Load something from the address in register aaa into register ccc
04 00100ccc aaaaaaaa cp [addr] r0; Store something in register ccc into address aaaaaaaa. (Not implemented)
05 00101ccc -----aaa cp [r1] r0; Store something in register ccc into the address stored in register aaa.
06 00110000 aaaaaaaa jmp addr; Jump to address aaaaaaaa.
07 00111000 aaaaaaaa jz addr; Jump if zero
07 00111001 aaaaaaaa jnz addr; Jump if not zero
07 00111010 aaaaaaaa je addr; Jump if equal
07 00111011 aaaaaaaa jne addr; Jump if not equal
07 00111100 aaaaaaaa jg addr; Jump if greater than
07 00111101 aaaaaaaa jge addr; Jump if greater than or equal to
07 00111110 aaaaaaaa jl addr; Jump if less than
07 00111111 aaaaaaaa jle addr; Jump if less than or equal to
08 01000rrr aaaaaaaa jsr addr; Jump to subroutine. Save return address into r
09 01001--- --rrr--- rts; Return from subroutine. Return to address in r
10 01010--- -------- nop
11 01011--- -------- nop
12 01100--- -------- nop
13 01101--- -------- nop
14 01110--- -------- nop
15 01111--- -------- nop
ALU Operations
16 10000ccc --aaabbb add r0 r1 r2 Add
17 10001ccc --aaabbb and r0 r1 r2 And
18 10010ccc --aaabbb or r0 r1 r2 Or
19 10011ccc --aaabbb xor r0 r1 r2 Xor
20 10100ccc --aaa--- not r0 r1 Not
21 10101ccc --aaa--- rsh r0 r1 RShift
22 10110ccc --aaa--- rshx r0 r1 XRShif
23 10111ccc --aaa--- cp r0 r1 Copy
24 11000--- --aaabbb scmp r0 r1 Signed Compare
25 11001--- --aaabbb ucmp r0 r1 Unsigned Compaire
26 11010--- -------- nop
27 11011--- -------- nop
28 11100--- -------- nop
29 11101--- -------- nop
30 11110--- -------- nop
31 11111--- -------- nop
Example Program
;
;
; Set all RAM to -1
;
;
; %r0 constant -1
; %r1 write pointer.
; %r2 constant 1
; %r3 constnat 256
cp %r0 -1
cp %r1 [minMem] ; 128 is the first byte of RAM.
; RAM goes from 128 to 255
cp %r2 1
cp %r3 [maxMem] ; Load from ROM. load immediat can only load -128 to 127 with sign extension
loop: cp [%r1] %r0 ; Copy -1 to the %r1 pointer
add %r1 %r1 %r2 ; Add 1 to the write pointer
ucmp %r1 %r3
jl loop ; jump while %r1 < %r3
end: jmp end
maxMem: .num 256
0 minMem: .num 128
; Assembled output
;00 00001 000 11111111
;01 00010 001 00001010
;02 00001 010 00000001
;03 00010 011 00001001
;04 00101 000 00001000
;05 10000 001 00001010
;06 11000 000 00001011
;07 00111 110 00000100
;08 00110 000 00001000
;09 00000001 00000000
;10 00000000 10000000
You can download the assembler from:
http://pastebin.com/FbbCfcwU
| Progress | 100% complete |
| Tags |
2 Update Logs
Computer Release V1.1 : by Challenger2 04/09/2012 10:52:27 amApril 9, 2012 @ 2:52 pm UTC
I have released the fully operational CPU. The CPU has new registers and RAM designs that seem to have fixed the timing issues. Master-Slave flip-flips do not get along with enable signals. I was able to get a pulse triggered D-Latch to work by putting lots of repeaters on the input side of the latch. The only Master-Slave register in the CPU is now the instruction register.
I have added LOTs of signs all over the place describing what the CPU does and how it works. Look for the Diamond platforms throughout the computer. I hope it makes the computer more understandable.
The CPU is currently running a program puts a memory address number into that very same address. EX. Write 200 to RAM address 200, 201 to RAM address 202, ETC. The CPU is about 2/3s down RAM bank 1. Just turn on the main clock and the CPU should start writing away.
I have added LOTs of signs all over the place describing what the CPU does and how it works. Look for the Diamond platforms throughout the computer. I hope it makes the computer more understandable.
The CPU is currently running a program puts a memory address number into that very same address. EX. Write 200 to RAM address 200, 201 to RAM address 202, ETC. The CPU is about 2/3s down RAM bank 1. Just turn on the main clock and the CPU should start writing away.
Current Program
;000 0001010100001000 cp %r5 [MAXRAM]
;001 0000111000000001 cp %r6 1
;002 0001011100001001 cp %r7 [MINRAM]
;003 0010111100111000 start: cp [%r7] %r7
;004 1000011100111110 add %r7 %r7 %r6
;005 1100000000111101 ucmp %r7 %r5
;006 0011111000000011 jl start
;007 0011000000000111 end: jmp end
;008 0000000100000000 MAXRAM: .num 256
;009 0000000010000000 MINRAM: .num 128
;001 0000111000000001 cp %r6 1
;002 0001011100001001 cp %r7 [MINRAM]
;003 0010111100111000 start: cp [%r7] %r7
;004 1000011100111110 add %r7 %r7 %r6
;005 1100000000111101 ucmp %r7 %r5
;006 0011111000000011 jl start
;007 0011000000000111 end: jmp end
;008 0000000100000000 MAXRAM: .num 256
;009 0000000010000000 MINRAM: .num 128
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Have something to say?
What are you doing with yourself right now ?
So long as the program needs less than 64 instructions and 128 words of RAM your good.
I would really like to hear more about your Assembler . .does it accept python as source or byte code ?
In Redstone,
I can imagine how implementing instruction 00100 might bring convolution to the device physically, but it would sure bring clarity to it's assembly programmers ... I'm certain it's not beyond your ability to implement genteelly.
Also I'm curious:
1). How did you come across such an elegant instruction set architecture . .?
2). How old are you!
and 3). What do you like working on besides Minecraft?
It's a pleasure to welcome you to Planetminecraft, i will be keeping an eye on you !
The assembler does not accept python or byte code as input. The assembler is written in python and accepts assembly code as input. The assembly code is pretty stripped down and unique to the Cloud Computer. The assembler will output the assembled program so you can manually code it into the RAM (OR RAM if you _REALLY_ wanted to.) The assembler DOES accept named labels, so you can jump to named locations in the code.
Instruction 00100, or store absolute, is an easier instruction to implement than the store register indirect instruction which is already implemented. I did the register indirect version first because I wanted to test out the new RAM bank. The instruction can be easily coded into the FPGA style instruction decoder. All I have to do is put torches in the right place. (Although finding the right places and testing can take a lot of time)
The instruction set is fully custom and designed for the Cloud Computer even before I started it. The instruction set is somewhat inspired by the MIPS and RISK instruction sets where you can do an ALU OP on any two registers and store the result into any register. It works well in MC as you can do an entire ALU op in one cycle if you use instruction pre-fetch. (The Cloud Computer does have instruction pre-fetch :) Actually, the load and store instructions take 2 cycles and the jump instructions take 2 cycle if you jump and 1 cycle if you don't. All other instructions pipeline to 1 instruction per clock )
The instruction set is pretty much the minimum you need to make a modern style computer work. It has two addressing modes for load and store instructions, basic ALU operations, and branch control. The register indirect address mode is very important, so I had to have those instructions, even though they were hard to do. Without them, you can't make an array.
I like driving driving my sports car, Linux, and software engineering.
I know some Python, C, C++, a little Java, Visual Basic 6.0, Visual Basic .NET, C#, Ladder Logic, Shell scripting, and a little Perl on the side.
I'm a professional software engineer by trade.
I'll have a download of the CPU up once I fix the store absolute instruction.
I also really enjoy using most of those programming languages you mentioned, except ofcoarse Ladder Logic :P
I'm a software engineer too ( No surprise ), i make data-base translators for my income, but my real love for programming comes from games : )
I did get a little confused about your Assembler program, you see i have also written a machine-code translator in Lua a 'dynamic language' very similar to Python, I'm currently working on a compiler and was thinking alot about that when i spotted this rather amazing project.
Can't wait to try this thing; so hurry up and place those torches : ) !
really really really nice work btw ; )